A Fast Constant Coefficient Multiplier for the XC6200

We discuss the design of a high performance constant coefficient multiplier on the Xilinx XC6200 FPGA. The dynamic reconfiguration capabilities of the device are used to allow the constant coefficient to be rapidly changed. The design also provides better performance and density than similar multipliers on state of the art conventional FPGA’s which require complete reconfiguration to change the coefficient. Introduction The Xilinx XC6200 [1] is the first commercial FPGA specifically designed to work in close cooperation with a microprocessor. To the microprocessor the XC6200 appears as a block of RAM, configuration data and registers within the user design appear within this memory space. The data bus width is programmably selectable to 8,16 or 32 bits. Additional features support writing many words of configuration memory with the same data simultaneously (to reduce configuration time) and grouping nonadjacent registers within the user design into a single word for transfer to and from the processor. XC6200 application development and debug is supported by the XACTStep Series 6000 CAD software package and by a PCI bus resident development system [2]. The XC6200 architecure is derived from the Algotronix CAL technology which Xilinx aquired in 1992 [3] [4]. Constant coefficient multiplication is a common function in many Digital Signal Processing (DSP) applications such as Finite Impulse Response (FIR) filtering. In this case the constant coefficients represent filter parameters and are changed much less frequently than the input data values. The multiplier described here multiplies an 8-bit input number by a constant 8-bit coefficient to get a 16-bit result, the numbers are unsigned. An efficient technique to implement fixed coefficient multipliers of FPGA’s using Look Up Table (LUT) based FPGA’s was developed by Xilinx [5]. This relies on lookup tables, rather than a network of adders, to perform most of the multiplication. For example, there are 16 possible results when a four bit number is multiplied by an 8 bit fixed number (because there are 16 different four bit numbers). Thus a four bit variable times eight bit constant mu ltiplier can be implemented by a 16 entry lookup table. Each entry must be 12 bits, the width of the largest possible output. An 8-bit by 8-bit constant multiplier can be built using two of these 4-bit by 8-bit constant multipliers in the configuration shown in figure 1. Figure 2 explains the simple mathematics behind this arrangement. Figure 1: LUT Based Multiplier LUTB Adder LUTA 8 bit Data 4 4